1. Field of the Invention
The present invention relates to digital systems and, more specifically to a controller for a digital memory.
2. Description of the Prior Art
Many computer servers use a smart re-power chip connected to main memory to realize large system memory capacities. As memory technology advances and system capacities increase, the initial program load (IPL) time required to initialize all of main memory increases. The smart re-power chips are sometimes used to drive multiple dual in-line memory module (DIMM) loads or, in the case of a fully buffered DIMM, reside on the DIMM itself. The DIMM could be a single rank, dual rank, quad rank, or possibly more than 4 ranks of dynamic random access memory (DRAM) modules.
In existing systems, a smart redrive chip simply passes write commands with data through to the memory DIMMs. With this method, the DIMM bus data and command conflicts needed to be considered when making the decision to dispatch the command and data from the controller. Newer technology allows splitting writes into two transactions. By incorporating data buffering capability within the smart redrive chip, the write commands are split into two commands, one to fill the redrive chip's data buffer and the second to push the data out to the memory DIMM. This allows more efficient scheduling of the command bus by removing the scheduling dependency on the memory bus. Write data can be written to a buffer on the redrive chip, then pushed to the memory DIMM at a later time when it has a lesser effect on memory reads. Because writes are typically not as critical as reads are, and because the data can be filled into the buffers in advance of performing the writes (tucked under other operations), the high speed bus may have a reduced data width that is not capable of streaming continuous memory writes (since typical command traffic will have more reads than writes).
In one example of a redrive chip, the high speed bus from the memory controller to the redrive chip is a combined command/data bus that requires 32 transfers at a 2 Gb/s data rate to fill the buffers. This amount of data requires only four transfers at 533 Mb/s on the memory bus to the DIMMs. Thus, the high speed bus cannot source enough data to stream writes continually.
Therefore, there is a need for a system that sources initialization data to DIMMs in a continuous manner.